Manufacturing processes for semiconductor devices and Integrated Circuits (ICs) (including semiconductor devices) include a number of lithographic processes to transfer geometric patterns representing the design layout of the different features of a semiconductor device or an IC from reticles or lithographic masks to a light-sensitive chemical (known as photoresist or resist) on a surface of a semiconductor wafer or die to form masks on the semiconductor wafer. The layout patterns on the wafer as defined by the masks are then used in subsequent process steps to manufacture the semiconductor device or IC. In a complex IC (for example, a CMOS IC), the wafer will go through a lithographic process up to 50 times.
In optics, the Depth of Focus (DoF) is the distance in front of and beyond the subject that appears to be in focus. In the manufacture of semiconductor devices and ICs, the layout patterns of the features of the semiconductor device including all the smaller features (for 32 nm technology, the smaller features include the contact holes which will be in the range of 50-60 nm after lithography) are transferred to the wafer using lithographic processes. Illumination conditions of the lithographic processes are chosen to balance DoF as well as exposure latitude and the illumination conditions include parameters such as wavelength of light used, size of lens aperture and other parameters of the lithographic equipment.
For features which are to be formed in the same layer of the wafer and which require layout patterns on the lithographic mask which look different or have different densities or pitches (the pitch being the distance between adjacent layout patterns), for a single exposure using a single illumination condition, the process window or Depth of Focus (DoF) for such a lithographic mask is small and is limited by the number of different pitches. For example, the illumination conditions, such as wavelength of light used, and size of lens aperture, for a lithographic mask comprising only a dense regular pattern can be optimised for the dense regular pattern to provide a large process window or DoF and similarly the illumination conditions for a lithographic mask comprising only isolated patterns can be optimised for the isolated patterns to provide a large process window or DoF. However, for a combination of dense regular patterns and isolated patterns on a single lithographic mask for the same layer of the wafer, a compromise in the illumination conditions has to be made which reduces the size of the process window or DoF.
As the dimensions of the design layout patterns on the lithographic mask decrease, the DoF decreases and there is a limit to the DoF below which lithographic techniques cannot be used to transfer features of a semiconductor device to a surface of a wafer. With the trend to shrink the size of devices which results in the reduction of the dimensions of features, it is becoming harder to print small features, such as contact holes, vias, connection lines, using lithographic techniques due to the limit of the DoF and achievable resolution.
Different techniques have been developed to maximise the size of the process window or DoF, in particular for layout patterns in the same layer having different pitches or incompatible densities. For example, one technique uses a double patterning method in which two lithographic masks are used along with two exposures under different illumination conditions and two etch steps. In the example given above, one of the masks is used to transfer the dense regular patterns to the wafer and the other mask is used to transfer the isolated patterns. However, with this method two lithographic masks and two etch steps are required which increases the cost of such a process. Furthermore for features having small dimensions, such as contact holes, which require critical masks, the requirement of two critical masks significantly increases the manufacturing costs. U.S. Pat. No. 6,498,105 describes a double patterning method.
Another technique uses a double exposure method in which one resist layer on the wafer is exposed at two different times with different lithographic masks. This allows for the illumination conditions to be optimised for the different lithographic masks but does not require additional resist layers nor additional etch steps. However, as with the double patterning method, the double exposure method requires two masks which increases the manufacturing costs and multiple passes in order to produce the layout pattern on the wafer which reduces through put. In addition, the combination of the two exposures cannot improve the minimum resolution limit which results in over sized contact holes.
U.S. Pat. No. 6,784,005 discloses using a photoresist reflow process to shrink isolated and random contact openings so that each of the contact openings have substantially the same critical dimension and to thereby enhance the resolution and the DoF of the contacts.
There is therefore a need for an improved method of forming openings, such as contact holes, in semiconductor devices.